1. Field of the Invention
The present invention relates to an in-plane switching liquid crystal display (IPS-LCD) and, more particularly, to an IPS-LCD with a redundancy structure for an opened common electrode line and a high storage capacitance.
2. Description of the Related Art
Twisted nematic liquid crystal display devices (TN-LCDs) having high image quality and low power consumption are widely applied to flat panel display devices. The TN-LCD, however, has a narrow viewing angle due to refractive anisotropy of liquid crystal molecules. To solve this problem, a multi-domain TN-LCD and a TN-LCD including an optical compensation film have been introduced. In such LCDs, however, contrast ratio is decreased and color shift is generated depending on viewing angle. Further, for the purpose of a wide viewing angle, an in-plane switching LCD (IPS-LCD) is also proposed, which is suggested to materialize wide viewing angle.
Recently, compared with the conventional TN-LCD, a drawback regarding to the transmittance is found in the IPS-LCD, and thus several of pixel structures have been developed for achieving a higher solution in the IPS-LCD. In one case, a resin insulator is formed between a signal line and a common electrode line to decrease the delay time of the signal line and minimize the coupling capacitance between the signal line and the common electrode line.
FIG. 1A is a plan view of a pixel structure of a conventional IPS-LCD. FIG. 1B is a sectional view according to line Ixe2x80x94I of FIG. 1A. The IPS-LCD comprises a pair of glass substrates 12 and 14, and a liquid crystal layer 16 formed in a space between the two glass substrates 12 and 14. On the bottom glass substrate 12, a plurality of gate lines 18 and a plurality of signal lines 20 are perpendicularly arranged in a matrix form to define a plurality of pixels 22. In the pixel 22, a common electrode line 24 extends parallel to the signal lines 20 and overlaps the signal line 20, a thin film transistor (TFT) structure 26 is formed adjacent a cross point of the gate line 18 and the signal line 20, and a pixel electrode 28 is parallel to the common electrode line 24 in the center of the pixel 22.
The TFT 26 includes a gate electrode 26A protruded from the gate line 18, a gate insulating layer 19 formed on the gate electrode 26a, a channel layer 26b formed on the gate insulating layer 19, a source electrode 26c electrically coupled the signal line 20, and a drain electrode 26d electrically coupled one extension of the pixel electrode 28 through a via hole 27.
The ends of the common electrode lines 24 are electrically connected to a common bus line (not shown) that is a rectangular loop in the peripheral area of the bottom glass substrate 12. The other extension of the pixel electrode 28 is a bar 30 parallel to the gate line 18 and overlapping a predetermined area of the gate line 18, causing a storage capacitor structure. In general, the storage capacitor structure is applied to prevent the IPS-LCD 10 from a gray inversion, a flicker, and an afterimage. Also, the common electrode line 24, the pixel electrode 28 and the bar 30 are patterned on the same plane by using a transparent material, such as ITO or IZO.
Further, a passivation layer 21 is deposited to cover the gate insulating layer 19 and the signal lines 20, and a resin insulator 32 is formed between the passivation layer 21 and the common electrode lines 24. This resin insulator 32 decreases the delay time of the signal line 20, and minimizes the coupling capacitance between the signal line 20 and the common electrode line 24.
On the upper glass substrate 14, a black matrix 34 is formed to prevent light leakage generated from the TFT 26, the gate line 18, and the signal line 20. A color filter layer 36 and an over-coat layer 38 are formed on the black matrix 34 in sequence. In addition, a first alignment layer (not shown) and a second alignment layer (not shown) are formed on the inner surface of the bottom glass substrate 12 and the upper glass substrate 14, respectively, thus the liquid crystal layer 16 is filled between the two alignment layers.
The pixel structure with the resin insulator 32 of the IPS-LCD 10, however, has a drawback that different voltages are applied to the common bus line when a line defect is found in the common electrode line 24. FIG. 2A is a circuit diagram showing an opened common electrode line according to the pixel structure of FIG. 1A. FIG. 2B is a circuits diagram showing different resistances and voltage applied to the opened common electrode line of FIG. 2A. As shown in FIG. 2A, the ends of the gate lines 18 are electrically connected to gate pads 18a, and the ends of the signal lines 20 are electrically connected to signal pads 20a. Also, the end of the common electrode lines 24 are electrically connected to a common bus line 24a in the peripheral area. When a line defect point A is found in the common electrode line 24, the common electrode line 24 is opened. As shown in FIG. 2B, since the resistance of ITO is over about 200xcexa9, a first section 24I of a smaller length in the opened line has a smaller resistance R1, and a second section 24II of a greater length in the opened line has a larger resistance R2. Therefore, the voltage V1 applied to the first section 24I and the voltage V2 applied to the second section 24II are different, resulting in a great impact on an electrical performance of the IPS-LCD 10.
The present invention is an IPS-LCD with a redundancy structure for an opened common electrode and a high storage capacitance.
The IPS-LCD comprises a first substrate and a second substrate parallel to each other, and a liquid crystal layer disposed in a space between the first substrate and a second substrate. A plurality of gate lines and a plurality of signal lines are perpendicularly arranged in a matrix form on the first substrate to define a plurality of pixels. A plurality of TFTs is formed in the plurality of pixels, respectively. A redundancy pattern comprises a plurality of common electrode lines extending parallel to the signal lines and a plurality of common bus lines extending parallel to the gate lines, in which the common electrodes overlap the signal lines respectively, the common bus lines overlap the gate lines respectively, and the common bus lines are electrically connected to the common electrode lines. A plurality of pixel electrodes are disposed parallel to the common electrode lines in the plurality of pixels, respectively. A plurality of complementary electrode patterns is formed in the plurality of pixels respectively. An insulator is sandwiched between the common electrode lines and the signal lines. The signal lines and the complementary electrode patterns are formed on the same plane, the common electrode lines, and the pixel electrodes and the common bus lines are patterned on the same plane.
Accordingly, it is a principal object of the invention to provide means to achieve a higher resolution.
It is another object of the invention to decrease the delay time of the signal line.
Yet another object of the invention is to minimize the coupling capacitance between the signal line and the common electrode line.
It is a further object of the invention to provide two storage capacitor structures to achieve a higher capacitance.
Still another object of the invention is to provide a redundancy structure for an opened common electrode line.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.